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SH67P54
OTP 4-Bit Micro-controller with LCD Driver
Features
LCD shared as LED Matrix SH6610D-Based Single-Chip 4-Bit Micro-controller Built-in Dual Tone PSG with One Noise Generator OTPROM: 4K X 16 bits Built-in Watchdog Timer RAM: 384 X 4bits - System Register: 48 X 4 bits Two LVR Level (Code Option) - Data RAM: 336 X 4 bits - Level1: 4.0V - Level2: 2.5V Operation Voltage: System Oscillator = 300kHz - 4MHz, VDD = 2.4V - 6.0V 2 Clock Sources System Oscillator = 30kHz - 8MHz, VDD = 4.5V - 6.0V OSC: (Code Option selects the type of OSC) - Crystal Oscillator: 32.768kHz 16 CMOS Bi-directional I/O Pins (PORT C, D can switch to segment) - RC Oscillator: 262kHz Built-in Pull-high and Pull-low Resistor for I/O OSCX: (system register selects the type of OSCX) 8-Level Subroutine Nesting (include interrupts) - Ceramic Resonator/Crystal Oscillator: 400kHz - 8MHz One 8-Bit Auto Re-load Timer/Counter - RC oscillator: 2MHz - 8MHz Warm-Up Timer for Power-on Reset Instruction cycle time: Powerful Interrupt Sources: - 122.07s for 32.768kHz - External Rising/Falling Interrupt - 15.27s for 262kHz - Timer0 Interrupt .com - 8.79s for 455kHz - Base Timer Interrupt - 2s for 2.0MHz - Port's Rising/Falling Edge Interrupt: PORTB, C - 0.5s for 8.0MHz 8-bit Base Timer User program can read ROM data LCD Driver: 8 X 30 (1/8 duty 1/4 bias), 6 X 32 (1/6 duty 1/3 bias), Two low power operation modes: HALT and STOP 5 X 33 (1/5 duty 1/3 bias), 4 X 34 dots (1/4 duty 1/3 bias) Low power consumption LCD used as Scan Output OTP type & Code protection
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General Description
SH67P54 is a single chip micro-controller integrated with SRAM, 4K OTPROM, timer, watchdog timer and dual-tone PSG, LCD driver, LED Matrix driver and I/O port.
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SH67P54
QFP64 PIN Configuration
COM8/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
COM4
COM3
COM2
COM1
NC
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 32 31 30 29 28 27 V1 V2 V3 V4 NC RESET TEST OSCO OSCI OSCXO OSCXI VDD GND
SH67P54
NC 26 25 24 23 22 21 20
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SEG11 SEG10 SEG9
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PORTC.3/SEG4 PORTC.2/SEG3 PORTC.1/SEG2 PORTC.0/SEG1 PORTB.3 PORTB.2 PORTB.1
14 15 16 17 18 19
NC
PORTD.3/SEG8
PORTD.2/SEG7
PORTD.1/SEG6
PORTD.0/SEG5
PORTB.0
PORTA.3
PORTA.2
PORTA.1
PORTA.0
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Pad Configuration
COM8/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
SEG25
SEG27
SEG29
SEG26
SEG28
SEG30
COM4
COM3
COM2
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
42 41 40 39 38 37 36 35 34 33 32 31 30 29
COM1
28 27 26 25 24 23 22 21
V1 V2 V3 V4 RESET TEST OSCO OSCI OSCXO
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19 OSCXI 18
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SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
VDD
BD1 BD0
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GND 17
1 PORTD.3/SEG8
2 PORTD.2/SEG7
3 PORTD.1/SEG6
4 PORTD.0/SEG5
5 PORTC.3/SEG4
6 PORTC.2/SEG3
7 PORTC.1/SEG2
8 PORTC.0/SEG1
9 PORTB.3
10 PORTB.2
11 PORTB.1
12 PORTB.0
13 PORTA.3
14 PORTA.2
15 PORTA.1
16 PORTA.0
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Block Diagram
ROM (4096 X 16) RAM (384 X 4) OSCS SH6610D CPU CORE PORTA & EXTERNAL INT 8-BIT TIMER0 OSCI OSCO OSCXI OSCXO PORTA.0 (INT0) PORTA.1 (PSG) PORTA.2 (PSG) PORTA.3 PORTB [3:0] PORTC [3:0] PORTD [3:0] SEG [30:9] (SEG[8:1] shared with PORTC &PORTD) COM [4:1] (COM[8:5] shared with SEG[31:34])
I/O PORT LCD RESET RAM SCAN REGISTER PSG COMMON SEGMENT
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GND
DRIVER CPU OPERATING VOLTAGE DRIVER
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V1 V2
V3
V4
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Pad Description
Pad NO. 1, 2, 3, 4 5, 6, 7, 8 9, 10, 11, 12 13, 14, 15, 16 17 18 19 20 21 22 23 24 25, 26, 27, 28 32, 31, 30, 29 33, 34, 35, 36 37 - 58 Designation PORTD [3:0] PORTC [3:0] PORTB [3:0] PORTA [3:0] GND BD0 VDD BD1 OSCXI OSCXO OSCI OSCO TEST RESET V [4:1] COM [4:1] COM5/SEG34, COM6/SEG33, COM7/SEG32, COM8/SEG31 SEG [30:9] I/O I/O I/O I/O I/O P I P I I O I O I I I O Description Bit programmable I/O, shared with Segment 8 - 5 Bit programmable I/O, shared with Segment 4 - 1 Bit programmable I/O, Vector interrupt Bit programmable I/O, PORTA.1, PORTA.2 shared with PSG output Ground Bonding option 0 Power supply Bonding option 1 Oscillator X input Oscillator X output Oscillator input Oscillator output Test pin must be connected to GND Reset input (No internal pull-high) Connected with external LCD divided resistor Common signal output for LCD display
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O.com signal output for LCD display Common/segment O Segment signal output for LCD display, Shared with scan output
Total: 58 Pads, 2 bonding Pads.
OTP Programming Pin Description (OTP program mode)
Pad NO. 18 24 17 21 16 Designation VDD VPP GND SCK SDA I/O P P P I I/O Shared by VDD RESET GND OSCI PORTA.0 Description Programming Power supply (+5.5V) Programming high voltage Power supply (+11.0V) Ground Programming Clock input pin Programming Data pin
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Functional Description
1. CPU 1.4. Table Branch Register (TBR) The CPU contains the following functional blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Table Data can be stored in program memory and can be Accumulator, Table Branch Register, Data Pointer (INX, DPH, referenced by using Table Branch (TJMP) and Return DPM, and DPL) and Stacks. Constant (RTNW) instructions. The TBR and AC are placed 1.1. PC by an offset address in program ROM. TJMP instruction branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The The PC is used for ROM addressing consisting of 12-bits: address is determined by RTNW to return look-up value into Page Register (PC11), and Ripple Carry Counter (PC10, (TBR, AC). ROM code bit7-bit4 is placed into TBR and PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). bit3-bit0 into AC. The program counter is loaded with data corresponding to 1.5. Data Pointer each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. The Data Pointer can indirectly address data memory. The program counter cans only 4K program ROM address. Pointer address is located in register DPH (3-bits), DPM (Refer to the ROM description). (3-bits) and DPL (4-bits). The addressing range can have 1.2. ALU and CY 3FFH locations. Pseudo index address (INX) is used to read or write Data memory, then RAM address bit9 - bit0 comes The ALU performs arithmetic and logic operations. The ALU from DPH, DPM and DPL. provides the following functions: 1.6. Stack Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) The stack is a group of registers used to save the contents of Decimal adjustments for addition/subtraction (DAA, DAS) CY & PC (11-0) sequentially with each subroutine call or Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) interrupt. The MSB is saved for CY and it is organized into 13 Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC) bits X 8 levels. The stack is operated on a first-in, last-out Logic Shift (SHR) basis and returned sequentially to the PC with the return The Carry Flag (CY) holds the ALU overflow that the instructions (RTNI/RTNW). arithmetic operation generates. During an interrupt service or Note: CALL instruction, the carry flag is pushed into the stack and .com The stack nesting includes both subroutine calls and recovered from the stack by the RTNI instruction. It is interrupts requests. The maximum allowed for subroutine unaffected by the RTNW instruction. calls and interrupts are 8 levels. If the number of calls and 1.3. Accumulator (AC) interrupt requests exceeds 8, then the bottom of stack will be The accumulator is a 4-bit register holding the results of the shifted out, that program execution may enter an abnormal arithmetic logic unit. In conjunction with the ALU, data is state. transferred between the accumulator and system register, or data memory can be performed. 2. OTPROM The ROM can address 4096 X 16 bits of program area from $000 to $FFF. 2.1. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. Address $000 $001 $002 $003 $004 Instruction JMP* JMP* JMP* JMP* JMP* Remarks Jump to RESET service routine Jump to External interrupt service routine Jump to Timer0 service routine Jump to Base Timer service routine Jump to PORT interrupt service routine
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*JMP instruction can be replaced by any instruction.
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3. RAM Built-in RAM contains of general-purpose data memory and system register. Because of its static nature, the RAM can keep data after the CPU enters STOP or HALT. 3.1. RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory allocation map: System register and I/O: $000 - $01F, $370 - $377 Data memory: $020 - $16F LCD RAM space: $300 - $348 Segment scan output RAM: $358 - $36D 3.2. Configuration of System Register: System Register $00-$1F, $370 - $377 RAM Map: Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C PAM2 $0D $0E $0F $10 $11 $12 $13 LVD TBR.3 INX.3 DPL.3 PULLEN PAM1 O/S2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 PH/PL O/S1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 PBCFR O/S0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 EINFR Bit3 IEX IRQX TM0.3 BTM.3 TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 Bit2 IET0 IRQT0 TM0.2 BTM.2 TL0.2 TH0.2 LCDON PA.2 PB.2 PC.2 PD.2 Bit1 IEBT IRQBT TM0.1 BTM.1 TL0.1 TH0.1 RLCD1 PA.1 PB.1 PC.1 PD.1 BD 1 Bit0 IEP IRQP TM0.0 BTM.0 TL0.0 TH0.0 RLCD0 PA.0 PB.0 PC.0 PD.0 BD 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Base timer mode register Timer0 load/counter register low nibble Timer0 load/counter register high nibble Reserved Bit0, 1: Select LCD divider resistors Bit2: LCD on/off PORTA Remarks
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R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W PORTB PORTC PORTD
Bit0, 1: Bonding option. BD0 is weakly pulled high BD1 is weakly pulled low Bit2, 3: PORTA.1 & PORTA.2 as PSG output or I/O PORT Bit0: Set PORTC as LCD segment Bit1: Set PORTD as LCD segment Bit2: Set segment as output port Bit3: LCD Voltage degrade Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Bit0: External interrupt (PORTA.0) rising/falling edge set Bit1: PORTB, PORTC interrupt rising/falling edge set Bit2: Port pull-high/low set Bit3: Port pull-high/low enable control Bit0: Turn on OSCX oscillator Bit1: CPU clocks select (1: OSCX/0: OSC) Bit3: OSCX type selection Bit0, 1: Select LCD DUTY (1/8, 1/6, 1/5 or 1/4) Bit2, 3: LCD frequency control
$14 $15
OXS LPS1
LPS0
OXM DUTY0
OXON DUTY1
R/W R/W
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The Configuration of System Register (continue) Address $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $370 $371 $372 $373 Bit3 PACR.3 PBCR.3 PCCR.3 PDCR.3 RDT.3 RDT.7 RDT.11 RDT.15 WDF SEL1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 Bit2 PACR.2 PBCR.2 PCCR.2 PDCR.2 RDT.2 RDT.6 RDT.10 RDT.14 WDT.2 SEL0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 Bit1 PACR.1 PBCR.1 PCCR.1 PDCR.1 RDT.1 RDT.5 RDT.9 RDT.13 WDT.1 C2M C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN Bit0 PACR.0 PBCR.0 PCCR.0 PDCR.0 RDT.0 RDT.4 RDT.8 RDT.12 WDT.0 C1M C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W W W W W W W Remarks PORTA input/output control PORTB input/output control PORTC input/output control PORTD input/output control ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register Bit0 - 2: Watchdog timer control Bit3: Watchdog timer overflow flag Reserved Bit0, 1: PSG1, PSG2 mode control Bit2, 3: PSG1, PSG2 clock source selection PSG channel 1 low nibble PSG channel 1high nibble Bit3: channel 1 octave shift control PSG channel 2 nibble 1 or alarm output PSG channel 2 nibble 2 PSG channel 2 nibble 3 Bit3: channel 2 octave shift control Bit0, Bit1: Channel 1, 2 enable Bit2, Bit3: volume control
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$374 $375 $376 $377
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W
CH1EN
System Register $00 - $12. (Please refer to SH6610D User's manual) 3.3. System Register Initial State: Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 Bit 3 IEX IRQX T0M.3 BTM.3 T0L.3 T0H.3 PA.3 PB.3 Bit 2 IET0 IRQT0 T0M.2 BTM.2 T0L.2 T0H.2 LCDON PA.2 PB.2 Bit 1 IEBT IRQBT T0M.1 BTM.1 T0L.1 T0H.1 RLCD1 PA.1 PB.1 Bit 0 IEP IRQP T0M.0 BTM.0 T0L.0 T0H.0 RLCD0 PA.0 PB.0 Power On Reset /Pin Reset /Low Voltage Reset 0000 0000 0000 0000 xxxx xxxx -000 0000 0000 WDT Reset 0000 0000 uuuu uuuu xxxx xxxx -uuu 0000 0000
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3.3. System Register Initial State (continue): Address $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $370 $371 $372 $373 $374 $375 $376 $377 Bit 3 PC.3 PD.3 PAM2 LVD TBR.3 INX.3 DPL.3 PULLEN OXS LPS1 PACR.3 PBCR.3 PCCR.3 PDCR.3 RDT.3 RDT.7 RDT.11 RDT.15 WDF SEL1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 Bit 2 PC.2 PD.2 PAM1 O/S2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 PH/PL LPS0 PACR.2 PBCR.2 PCCR.2 PDCR.2 RDT.2 RDT.6 RDT.10 RDT.14 WDT.2 SEL0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 Bit 1 PC.1 PD.1 BD 1 O/S1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 PBCFR OXM DUTY1 PACR.1 PBCR.1 PCCR.1 PDCR.1 RDT.1 RDT.5 RDT.9 RDT.13 WDT.1 C2M C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN Bit 0 PC.0 PD.0 BD 0 O/S0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 EINFR OXON DUTY0 PACR.0 PBCR.0 PCCR.0 PDCR.0 RDT.4 RDT.8 RDT.12 WDT.0 C1M C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN Power On Reset /Pin Reset /Low Voltage Reset 0000 0000 00xx 0000 xxxx xxxx xxxx -xxx -xxx 0100 0-00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Reset 0000 0000 uuxx uuuu uuuu uuuu uuuu -uuu -uuu 0uuu u-0u uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 1000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00
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RDT.0 .com 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. 3.4. Others Initial State: Others Program Counter (PC) CY Accumulator (AC) Data Memory After any Reset $000 Undefined Undefined Undefined
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4. System Clock and Oscillator 4.1. Circuit Configuration SH67P54 has two on-chip oscillation circuits OSC and OSCX. OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ.262kHz) determined by the Code Option. This is designed for low frequency operation. OSCX also has two types: ceramic/crystal (Typ.455kHz) or RC (2MHz to 8MHz) to be determined by the software option. It is designed for high frequency operation. It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation clock. At the start of Power on reset, Pin reset and low power reset initialization, the OSC starts oscillation and OSCX is turned off. But at the start of WDT reset initialization, the OSC starts oscillation and OSCX remains the original state. Immediately after reset initialization, the OSC clock is automatically selected as the system clock input source. Oscillator Block Diagram
OSCI OSCO Low Frequency Clock Oscillator System clock Source Selector OSCXI OSCXO High Frequency Clock Oscillator
& Switching control System clock
Base Timer
Generator
CPU Clock
4.2. OSC Oscillation The OSC generates the basic clock pulses that provide the CPU and peripherals (Base Timer, LCD) with an operating clock.
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OSC Crystal Oscillator Type
10P-15 P 32.768kHz Crystal OSCO 10P-15 P
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OSCI
CHIP
OSC RC Oscillator Type
ROSC OSCI
102
CHIP
OSCO
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4.3. OSCX Oscillation OSCX has two clock oscillators. The software options select the Ceramic/Crystal or RC as the CPU's sub clock. If the OSCX is not used, it must be selected as a ceramic resonator and the OSCXI must be connected to GND. OSCX Ceramic/Crystal Oscillator Type
47P-100 P OSCXI
455kHz Ceramic OSCXO 47P-100 P
CHIP
OSCX RC Oscillator Type
ROSCX
OSCXI
102
CHIP
OSCXO
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4.4. Control of Oscillator The oscillator control register configuration is shown as follows: Address $14 Bit3 OXS Bit2 Bit1 Bit0
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OXON: OSCX oscillation on/off. 0: Turn-off OSCX oscillation 1: Turn-on OSCX oscillation OXM: switching system oscillator. 0: select OSC as system oscillator 1: select OSCX as system oscillator OXS: OSCX oscillator type selection 0: OSCX set as Ceramic Resonator/Crystal Oscillator 1: OSCX set as RC oscillator 4.5. Programming Notes It takes at least 5 ms for the OSCX oscillation circuit to turn on until the oscillation stabilizes. When switching the CPU system clock from OSC to OSCX, the user must wait a minimum of 5ms since the OSCX oscillation is running. However, the start time varies with respect to oscillator characteristics and the condition of use. Thus the wait time depends on the application. When switching from OSCX to OSC, the user should switch clock first then turn off OSCX. If switching from OSCX to OSC and turning off OSCX in one instruction, the OSCX turn off control will be delayed for one instruction cycle automatically to prevent CPU operation error. Following is the timing of system clock switching.
OSCX turn off OSCX turn on
OSCXO
OSCO
SYS CLOCK
High frequency operation Low frequency operation Warm-up time Switch from OSCX to OSC Switch from OSCX to OSC High frequency operation
Figure 1. Timing of System Clock Switching
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4.6. System Clock The system clock varies as the clock source changes. The following table shows the instruction execution time according to each frequency of the system clock source. OSCFREQ Cycle time 32.768kHz (OSC) 122.07 s 262kHz (OSC) 15.27 s 455kHz (OSCX) 8.79 s 2MHz (OSCX) 2 s 8MHz (OSCX) 0.5 s
5. Low Voltage Reset (LVR) The LVR function is to monitor the supply voltage and generate an internal reset in the device. It is typically used in AC line applications or large battery where large loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum. 5.1. Functions of the LVR Circuit The LVR function is selected by Code Option. The LVR circuit has the following functions: - It generates an internal reset signal when VDD VLVR - It cancels the internal reset signal when VDD > VLVR Here, VDD: power supply voltage, VLVR: LVR detect voltage, there are two level selected by Code Option: Level1: 2.4 - 2.6V, typical 2.5V Level2: 3.8 - 4.2V, typical 4.0V
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6. I/O Ports
The MCU provides 16 bi-directional I/O pins. Each I/O pin contains pull high/low MOS controllable through programming. When every I/O is used as input, the PORT control register (PACR, PBCR, PCCR, PDCR) controls the ON/OFF of the output buffer. Every I/O pin has an internal pull high/low resistor, which is controlled by PULLEN, PH/PL of $13 and data of the port. Port I/O mapping address is shown as follows: Address $08 $09 $0A $0B $16 $17 $18 $19 Bit3 PA.3 PB.3 PC.3 PD.3 PACR.3 PBCR.3 PCCR.3 PDCR.3 Bit2 PA.2 PB.2 PC.2 PD.2 PACR.2 PBCR.2 PCCR.2 PDCR.2 Bit1 PA.1 PB.1 PC.1 PD.1 PACR.1 PBCR.1 PCCR.1 PDCR.1 Bit0 PA.0 PB.0 PC.0 PD.0 PACR.0 PBCR.0 PCCR.0 PDCR.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W PORTA PORTB PORTC PORTD PORTA input/output control PORTB input/output control PORTC input/output control PORTD input/output control Remarks
Equivalent Circuit for a Single I/O Pin
VDD PULLEN PH/PL VDD I/O CONTROL REGISTER OUTPUT HIGH MOSFET PULL HIGH MOSFET
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READ DATA IN READ
DATA REGISTER
I/O PIN
OUTPUT LOW MOSFET GND PULL LOW MOSFET GND
System Register $13 Address $13 Bit3 PULLEN Bit2 PH/PL Bit1 PBCFR Bit0 EINFR R/W Remarks
Bit0: External interrupt (PORTA.0) rising/falling edge set Bit1: PORTB, PORTC interrupt rising/failing edge set R/W Bit2: Port pull-high/low set Bit3: Port pull-high/low enable control
EINFR: 1: External Rising Edge interrupt 0: External Falling Edge interrupt PBCFR: 1: PORTB, PORTC Rising Edge interrupt 0: PORTB, PORTC Falling Edge interrupt PH/PL: 1: Port Pull high resistor ON 0: Port Pull low resistor ON PULLEN: 1: Port Pull high/low enable 0: Port Pull high/low disable To turn on the pull high resistor, user must set PULLEN to 1, set PH/PL to 1, and write 1 to the port data register. To turn on the pull low resistor, user must set PULLEN to 1, set PH/PL to 0, and write 0 to the port data register.
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6.1. PORTB & PORTC Interrupt The PORTB and PORTC are used as port interrupt sources. Following is the port interrupt function block-diagram.
PBCR.3 PORTB.3 PBCR.2 PORTB.2 PBCR.1 PORTB.1 PBCR.0 PORTB.0 PCCR.3 PORTC.3 PCCR.2 PORTC.2 PCCR.1 PORTC.1 PCCR.0 PORTC.0 PBCFR PBCR.3 PORTB.3 PORT INTERRUPT DETECT PORTINT
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PBCR.2 PORTB.2 PBCR.1 PORTB.1 PBCR.0 PORTB.0 PCCR.3 PORTC.3 PCCR.2 PORTC.2 PCCR.1 PORTC.1 PCCR.0 PORTC.0
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6.2. External INT0 PORTA.0 is shared by external interrupts. External INT0 (PORTA.0) AND PORTB, PORTC interrupt PROGRAMMING NOTES If user wants to generate an interrupt when a rising edge from GND to VDD emerges in the port, the following must be executed. 1. Set the port as input port, fill port data register and avoid port floating. 2. Pull low the port (Use external pull low resistor or set PULLEN to 1and set PH/PL to 0). 3. Set Rising Edge register. (Set PBCFR to 1 in PBC INT application. Set EINFR to 1 in EXINT application.) And further rising edge transition would not be able to make interrupt request until all of the pins return to GND in PBC INT application. If user wants to generate an interrupt when a falling edge from VDD to GND emerges on the port, the following must be executed. 1. Set the port as input port, fill port data register and avoid port floating. 2. Pull high the port (Use external pull high resistor or set PULLEN to 1and set PH/PL to 1). 3. Set Falling Edge register. (Set PBCFR to 0 in PORTB, PORTC INT application. Set EINFR to 0 in EXINT application). And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD in PBC INT application. When PORTC is shared to segment, user can only generate interrupt on PORTB.
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7. Timer 0 SH67P54 has one 8-bit timer. The timer consists of an 8-bit up counter and an 8-bit preload register. The timers provide the following functions: - Programmable internal timer function - Read the counter values 7.1. Timer 0 Configuration and Operation The timer 0 consists of an 8-bit write-only timer load register (TL0L, TL0H) and an 8-bit read-only timer counter (TC0L, TC0H). Each has low order digits and high order digits. The timer counter can be initialized by writing data into the timer load register (TL0L, TL0H). Write the low-order digit first and then the high-order digit. The timer counter is loaded with the content of the load register automatically when the high order digit is written or counts overflow happens. The timer overflow will generate an interrupt, if the interrupt enable flag is set. The timer can be programmed in several different system clock sources by setting the Timer Mode register (TM0). Timer 0 reads and writes operations follow these rules: Write Operation Low nibble first High nibble to update the counter Read Operation High nibble first Low nibble follows
7.2. Timer0 Mode Register (TM0) The 8-bit counter counts prescaler overflow output pulses. TM0 are 4-bit registers used for timer control as shown in Table 1. The register selects the input clock sources in the timer. Table 1. Timer0 Mode Registers ($02)
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TM0.3 -
TM0.2 0 0 0 0 1 1 1 1
TM0.1 0 0 1 1 0 0 1 1
TM0.0 0 0
Prescaler /2048 /128 /32 /8 /4 /2 /1
Clock Source System clock System clock System clock System clock System clock System clock System clock PORTA.0(Falling Edge)
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1 .com /512 1 0 1 0 1 1: Auto-Reload function
TM0.3 control function: 0: without Auto-Reload function
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8. Base Timer The MCU has a base timer which the clock source is OSC (Low frequency oscillation: Crystal 32.768kHz or RC 262kHz). After MCU is reset, it counts at every clock-input signal. When it counts to $FF, right after next clock input, counter counts to $00 and generates an overflow. This causes the interrupt of base timer interrupt request flag to 1. Therefore, the base timer can function as an interval timer periodically, generating overflow output as every 256th clock signal output. The timer accepts 4096Hz or 32.75kHz clock, and base timer generates an accurate timing interrupt. This clock-input source is selected by BTM register. Address $03 Bit3 BTM.3 1 Else states Bit2 BTM.2 0 Bit1 BTM.1 X X Bit0 BTM.0 X X Remarks Base timer mode register Enable the base timer Disable the base timer, clear base timer counters and keep them as $00 Clock Source 4096Hz or 32.75kHz 4096Hz or 32.75kHz 4096Hz or 32.75kHz 4096Hz or 32.75kHz
BTM.1 0 0 1 1
BTM.0 0 1 0 1
Prescaler Ratio /1 /4 /8 /16
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MPX
8 Bit base timer counter
32.768kHz or 262kHz
/8
4096Hz or 32.75kHz
4Bit Scaler
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BTM [3:2]
/1
/4
/8
/16
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9. Watchdog Timer (WDT) Watchdog timer is a down-count counter, and its clock source is an independent built-in RC oscillator, so that the WDT will always run even in the STOP mode (if it is enabled). The watchdog timer automatically generates a device reset when it overflows. Code Option can enable or disable this function. The watchdog timer control register (WDT bit2 - 0) selects different overflow frequency. WDT bit3 is watchdog timer overflow flag. If the Watchdog timer is enabled, the CPU will be reset when watchdog timer overflows. Repeat reads or writes WDT register ($1E), the watchdog timer should re-count before the overflow happens. System Register $1E: (WDT) Address $1E Bit 3 WDF X X X X X X X X 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X X Bit 2 WDT.2 Bit 1 WDT.1 Bit 0 WDT.0 R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R Remarks Bit2 - 0: Watchdog timer control Bit3: Watchdog timer overflow flag (Read only) Watchdog timer-out period = 4096ms Watchdog timer-out period = 1024ms Watchdog timer-out period = 256ms Watchdog timer-out period = 128ms Watchdog timer-out period = 64ms Watchdog timer-out period = 16ms Watchdog timer-out period = 4ms Watchdog timer-out period = 1ms No watchdog timer overflow reset Watchdog timer overflow, WDT reset happens
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0 1
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Note: Watchdog timer-out period valid for VDD = 5V. WDF will be cleared after Power on Reset, Pin Reset or Low Power Reset.
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10. LCD Driver The LCD driver contains a controller, a voltage generator, 8 common signal pins and 30 segment driver pins when LCD dots are maximum. There are four different programmable driving modes: 1/8 duty & 1/4 bias, 1/6 duty & 1/3 bias, 1/5 duty & 1/3 bias and 1/4 bias & 1/3bias. The driving modes are controlled by the system register $15 and the power-on initialization status is 1/8 duty, 1/4 bias. When 1/6 duty and 1/3 bias mode are used, COM7 - 8 are used as SEG32 - 31. When 1/5 duty and 1/3 bias mode are used, COM6 - 8 are used as SEG33 - 31. When 1/4 duty and 1/3 bias mode are used, COM5 - 8 are used as SEG34 - 31. The LCD SEG9 - 30 can also be used as output port controlled by the bit 2 of the system register $0D. When SEG9 - 30 are used as output ports, data must be written to bit 0 of the same addresses ($358 - $36D). LCD RAM could be used as data memory if necessary. When the "STOP" instruction is executed, the LCD will be turned off, but the data of LCD RAMs keep the same value before executing the "STOP" instruction. 10.1. LCD Control Register Address $15 Bit 3 LPS1 Bit 2 LPS0 Bit 1 DUTY1 Bit 0 DUTY0
DUTY1, 0: LCD duty control 0, 0: 1/8 duty, 1/4 bias 0, 1: 1/6 duty, 1/3 bias 1, 0: 1/5 duty, 1/3 bias 1, 1: 1/4 duty, 1/3 bias LPS1, LPS0: LCD frame frequency control. LCD clock is divided from OSC, so LCD frame frequency will change in proportion to the variation of OSC frequency.
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FRAME Frequency (OSC = 32.768kHz) IN 1/8 DUTY MODE IN 1/6 DUTY MODE IN 1/5 DUTY MODE IN 1/4 DUTY MODE
LPS1, LPS0
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1, 1 4Hz 4.2Hz 4.2Hz 4Hz
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32Hz 34.1Hz 34.1Hz 32Hz
0, 0
0, 1 16Hz 17.0Hz 17.0Hz 16Hz
1, 0 8Hz 8.5Hz 8.5Hz 8Hz
FRAME Frequency (OSC = 262kHz) IN 1/8 DUTY MODE IN 1/6 DUTY MODE IN 1/5 DUTY MODE IN 1/4 DUTY MODE
LPS1, LPS0 0, 0 256Hz 273Hz 273Hz 256Hz COM1 0, 1 128Hz 136Hz 136Hz 128Hz 1, 0 64Hz 68Hz 68Hz 64Hz 1, 1 32Hz 34Hz 34Hz 32Hz
COM1
ONE
FRAME
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When the CPU is in STOP mode, the COMx and SEGx are pulled low. It can easily be woken up by a keyboard scan (Port interrupt). When the CPU is in HALT mode, the COMx and SEGx are normal. It can easily be woken up by base timertimer0 or port interrupt.
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10.2. LCD Power
VDD Power Switch Power Degrade LCDON LVD LCD Power Supply Control Circuit LCD SEG1 segment driver OSC LPS0 LPS1 Pre-scaler LCDCLK DUTY0 DUTY1 Duty Control & scan output SEG34 LCD COM1 common driver COM8
Built-in special LCD power control for LCD power modulation. Address $0D Bit 3 LVD Bit 2 O/S2 Bit 1 O/S1 Bit 0 O/S0
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O/S2: Set LCD SEG9-SEG30 to be LCD segment output or scan output ports 0: LCD segment output 1: scan output ports. O/S1: Set PORTD as LCD segment or I/O PORT 0: I/O PORT 1: LCD segments. .com O/S0: Set PORTC as LCD segment or I/O PORT 0: I/O PORT 1: LCD segments. When LVD is set to 1 and the divider resistors is 270k, the LCD voltage power will be degraded to about 90% of VDD. It is designed to reduce extra LCD contrast control output pins. Then the LCD can be fitted automatically for different voltage levels by the software. 10.3. LCD on/off Control and Divider Resistors Setting Address $07 Bit 3 Bit 2 LCDON Bit 1 RLCD1 Bit 0 RLCD0
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LCDON: LCD on/off switch. 0: LCD off. 1: LCD on. * When LCD is off, COM & SEG output GND in LCD application. If LCD is off and LCD is shared to LED application, COM output VDD and SEG output GND. RLCD1, RLCD0: LCD divider resistors setting 0, 0: R1 = R2 = R3 = R4 = 270k (Default) 0, 1: R1 = R2 = R3 = R4 = 90k 1, 0: R1 = R2 = R3 = R4 = 30k 1, 1: R1 = R2 = R3 = R4 = 10k When large LCD panel is used, user can set the value of $07 to increase the bias current for better LCD performance. But it will cost more power, when smaller divider resistors are used. User can also use external parallel connection resistors for complex bias current.
VDD LCDON LVD Power Switch Power Degrade
V1
LCD Power Supply Control Circuit R1 R2 R3 R4
V2
V3
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V4
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10.4. Configuration of LCD RAM LCD 1/4 Duty, 1/3 Bias (COM1 - 4, SEG1 - 34) Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Address $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F $320 $321 Bit3 COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit2 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit1 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit0 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
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$30F $310
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LCD 1/5 Duty, 1/3 Bias (COM1 - 5, SEG1 - 33) Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F $320 Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Address $328 $329 $32A $32B $32C $32D $32E $32F $330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 $341 $342 $343 $344 $345 $346 $347 $348 Bit3 Bit2 Bit1 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33
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LCD 1/6 Duty, 1/3 Bias (COM1 - 6, SEG1 - 32) Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Address $328 $329 $32A $32B $32C $32D $32E $32F $330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 $341 $342 $343 $344 $345 $346 $347 Bit3 Bit2 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
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LCD 1/8 Duty, 1/4 Bias (COM1 - 8, SEG1 - 30) Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Address $328 $329 $32A $32B $32C $32D $32E $32F $330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 $341 $342 $343 $344 $345 Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
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SEG9 - 30 is used as scan output port Address $358 $359 $35A $35B $35C $35D Bit0 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Address $35E $35F $360 $361 $362 $363 Bit0 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 Address $364 $365 $366 $367 $368 $369 Bit0 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Address $36A $36B $36C $36D Bit0 SEG27 SEG28 SEG29 SEG30
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10.5. LCD Waveform
1/8 DUTY 1/4 BIAS SELECT UNSELECT V1 V2 V3 COM V4 GND SELECT UNSELECT V1 V2 SEG V3 V4 GND SEG SELECT UNSELECT COM 1/4 DUTY 1/3 BIAS SELECT UNSELECT V1 V2 V3 GND
V1 V2 V3 GND
Example the output waveform of 1/8 duty and 1/4 bias
V1 V2 COM1 V3 V4 GND
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V1 V2 COM2 V3 V4 GND
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V1 V2 COM3 V3 V4 GND
VDD V1 SEG V2 V3 GND
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Example 1/4 Duty 1/3 Bias
COM4 V3 COM1 COM3 V2 V1 0 V3 COM2 COM2 V2 V1 COM1 0 V3 COM3 V2 V1 0 V3 COM4 V2 V1 0 SEGn+1 SEGn SEGn V3 V2 V1 0
V V2
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SEGn+1
V1 0
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V3 .com V V1 COM4 - SEGn 0 -V1 -V2 -V3
10.6. Shared to LED Application User can use SEG & COM in the application of LED matrix by Code Option and configuration of LED RAM is the same as LCD RAM. Application Note The SEG & COM can not driver the LED matrix directly for the cause of weak driving ability. So in the LED Matrix application the driving circuit will be used such as following. Example 1/8 Duty LED Matrix Application Circuit.
VDD VDD VDD COM1 COM2 COM3 VDD COM8
COM1' SEG1' SEG2' SEG1 GND SEG2 GND SEG29 GND SEG30 GND
COM2'
COM3'
COM8'
LED Matrix 8X30 dots
SEG29' SEG30'
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10.7. LED Waveform
1/8 DUTY UNSELECT VDD 1/4 DUTY UNSELECT
VDD
COM SELECT SELECT SELECT VDD SELECT GND
COM SELECT SELECT SELECT SELECT GND VDD
SEG
SEG GND
UNSELECT
UNSELECT
GND
UNSELECT
UNSELECT
Example 1/4 Duty 4X10 Dots
COM1 COM2 COM3 COM4 VDD GND COM1' COM2' COM3' GND COM4'
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SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
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SEG1' SEG2' SEG3' SEG4'SEG5' SEG6'SEG7' SEG8' SEG9' SEG10'
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COMx' & SEGx'refer to the driving-amplified output of COMx & SEGx.
GND VDD
GND
11. Read ROM DATA Address $1A $1B $1C $1D Bit 3 RDT.3 RDT.7 RDT.11 RDT.15 Bit 2 RDT.2 RDT.6 RDT.10 RDT.14 Bit 1 RDT.1 RDT.5 RDT.9 RDT.13 Bit 0 RDT.0 RDT.4 RDT.8 RDT.12 R/W R/W R/W R/W R/W Remarks ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register
The RDT register consists of a 12-bit write-only PC address load register (RDT.11 - RDT.0) and a 16-bit read-only ROM table data read-out register (RDT.15 - RDT.0). To read out the ROM table data, users should write the ROM table address to RDT register first (high nibble first then low nibble), then after one instruction, the right data will put into RDT register automatically (write lowest nibble of address into $1A will start the data read-out action).
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12. Programmable Sound Generator (PSG) PSG has channel1 and channel2. The function block diagram is shown as follows:
CHANNEL1 OSC MPX OSCX CHANNEL2 CH1 CLK MIXER CH2 CLK PSG PSG
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The PSG function provides four sub functions for wide applications. Programmable Sound Two channels create programmable sound. Every channel can be programmed as follows: - Enable/Disable every channel sounds. - Select every channel sound frequency. - Two channel sounds are mixed into one PSG output. - The PSG output can be controlled at 4 volume levels. Fine Noise PSG can provide wide-band noise. The wide-band noise volume can be controlled at 4 volume levels. Alarm PSG can provide many alarm functions by the software. The alarm carrier frequency can be programmed individually. The alarm volume can be controlled at 4 volume levels. Remote Control The remote control is the only expandable application for PSG sound. Since the remote control frequency is 56.13kHz or .com 37.92kHz, the software can select the sound frequency. 12.1. PSG Sub Block Diagram MPX block diagram
SEL0 SEL1
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OSC
/2
CLOCK-SLECTOR
PSG CLocK
OSCX
/16
SEL1 0 0 1 1
SEL0 0 1 0 1
Clock Source OSC OSC/2 OSCX OSCX/16
OSC clock OSC = 32.768kHz OSC = 262kHz OSC = 32.768kHz OSC = 262kHz OSCX = 1.8MHz OSCX = 455kHz OSCX = 1.8MHz OSCX = 455kHz
PSG clock 32.768kHz 262kHz 16.384kHz 131kHz 1.8MHz 455kHz 112.5kHz 28.4kHz
The MPX block selects 4 clock sources as PSG clock that provides the two channel clock sources.
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Channel 1
CH1EN PSG CLOCK /8 SELECTOR DIVIDER 1 /2 CH1 OUT OCT1
REGISTER C1.6 ~ C1.0
OCT1 0 1 Channel 2
Scaling ratio 1 1/8
Channel 1 is constructed by a 7-bit pseudo random counter. Channel 1 is enabled/disabled by CH1EN. It creates either a sound frequency or an alarm carrier frequency or a remote carrier frequency
C2M CH2EN OCT2 NOISE GENERATOR
C2.14 ~ C2.0
SELECTOR
PSG
CLK
/8 SELECTOR
CH2 OUT
REGISTER C2.14 ~ C2.0
C2.14 ~ C2.8
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DIVIDER 2
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C2.3 ~ C2.0
C1M
1Hz 4Hz 8Hz 32Hz ENEVLOP ENEVLOP
OCT2 0 1
Scaling ratio 1 1/8
A 15-bit pseudo random counter, construct channel 2. Channel 2 is enabled/disabled by CH2EN It can be a 15-bit wide-band noise generator or a 7-bit sound generator. It can also create an alarm envelope signal.
C2M 0 1 x
C1M 0 0 1 CH1 is a Sound generator. CH1 is a Sound generator. CH1 is a Sound generator.
Remarks CH2 is a Sound generator. CH2 is a Noise generator. CH2 is an Alarm mode register.
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Mixer
TIME SLOT VOL0 VOL1 PA.1 I/O PSG CH1 OUT TIME SLOT CH2 OUT VOL CONTROL PSG PA.2 I/O PAM2 SELECTOR2 PORTA.2 SELECTOR1 PORTA.1
PAM1
The MIXER mixes CH1-OUT and CH2-OUT into one tone output to PORTA.1PORTA.2, when PAM1 = 1PAM2 = 1. Then the tone output is controlled by the volume control bit into 4 volume levels and in the end outputted by PSG. PORTA.1 & PORTA.2 are controlled by PAM1 & PAM2 PAM2 0 0 1 1 PAM1 0 1 0 1 PORTA.1: I/O PORT PORTA.1: PSG output PORTA.1: I/O PORT PORTA.1: PSG output Remarks PORTA.2: I/O PORT PORTA.2: I/O PORT PORTA.2: PSG output PORTA.2: PSG output
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SEL1 0 0 1 1 SEL0 0 1 0 1 Vol. control NO YES YES YES VOL1 VOL0 .com 0 0 1 1 0 1 0 1 Vol. Level 1 2 3 4
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Note: The user should not enable two PSG channels together to produce one tone; otherwise it will produce some unpredictable errors. If it is necessary to use 2 channels together (i.e.: to play two channel melody), do not allow score always is the same tones, then the unpredicted errors will not occur or user will ignore it.
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The Value N of Divider1 is Corresponding to the REG C1.6 - C1.0 or REG C2.14 - C2.8 as shown in the following Table: LSFR (C1.6 - C1.0) (C2.14 - C2.8) 01 02 04 08 10 20 41 03 06 0C 18 30 61 42 05 0A 14 28 51 23 47 0F 1E 3C 19 72 64 48 11 22 45 0B N 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 16 2C 59 33 67 4E 1D 3A 75 6A 54 29 53 27 4F 1F 3E 7D 7A 74 68 50 21 43 07 0E 1C 38 71 62 44 09 N 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 12 24 49 13 26 4D 1B 36 6D 5A 35 6B 56 2D 5B 37 5E 3D 7B 76 6C 58 31 63 46 0D 1A 34 69 52 25 N 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 4B 17 2E 5D 3B 77 6E 5C 39 73 66 4C 19 32 65 4A 15 2A 55 2B 57 2F 5F 3F 7F 7E 7C 78 70 60 40 N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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12.2. Function Description PSG as sound generator The programmable sound is one of the 4 working modes. The software designer can select up to 16 clock sources as PSG clock. And then select the CH1 and CH2 frequency divided value that is controlled by the value of REG C1.6 - C1.0 or C2.14 C2.8. The user can select the 4-volume level controlled by VOL0, VOL1. The music tone can output both PSG and PSG . The user also can control the OCT1, OCT2 bit that shifts the music tone 3 octaves. Example 1: CH1EN = CH2EN = 1 OSCX = 1.8MHz, SEL0 = SEL1 = 1 So PSG clock = 112kHz; Switch clock = 28kHz Vol. Clock = 112kHz Example 2: CH1EN = 0; CH2EN = 1 OSCX = 1.8MHz, SEL0 = SEL1 = 1 So PSG clock = 112kHz; Switch clock = 28kHz; Vol. Clock = 112kHz
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Example 3: CH1EN = CH2EN = 1
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OSC = 32.768kHz, SEL0 = SEL1 = 0 So PSG clock = 32.768kHz; Switch clock = 32.768kHz No vol. control, the VOL level is set to 4 by hardware, so software should set VOL0 = VOL1 = 1.
Note: For 32.768kHz operations, the volume control cannot be used, since the PWM multiplexing frequency is not high enough to switch sound! If a user wants to turn off the PSG completely, the software must disable both channels. The user should not turn off the PSG by zero waves from output. Both the CH1EN and CH2EN should be set to "0" for the low power operation mode. Example 4 If software designer wants to create C2 (Channel 1) mixed with F5 (Channel 2) sound (For the C2, F5 sound frequency please refer to Music Table 1 and Music Table 2), VOL level = 3.Then the user can select the suggestion as follows: (1) The user first selects CH1EN = CH2EN = 1, C1M = C2M = 0. (2) The user can select OSCX = 1.8MHz and SEL0 = SEL1 = 1, so the PSG CLK = 112.5kHz. (3) Then the user can select OCT1 = 1 and the value of channel 1 LSFR (C1.6 - C1.0) = 23, so the N = 108. Please see the Music Table 1.So the channel 1 sound frequency = 112.5kHz/8/(2 X 108) = 64.10Hz the C2 sound frequency. (4) Then the user can select OCT2 = 0 and the value of channel 2 LSFR (C2.8 - C2.14) = 4F, so the N = 81. Please refer to the Music Table 1.So the channel 2 sound frequency = 112.5kHz/1/(2 X 81) = 694.4Hz the F5 sound frequency . (5) Lastly, the user should select the VOL1 = 1 and VOL0 = 0, so the VOL level = 3.
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Note: The designer provides two crossing tables as an appendix since the designer prefers PSG clock = 32.768kHz or PSG clock = 112.5kHz. PSG as a Noise Generator Fine noise is created by CH2. If the user wants to create the single noise, then make the CH1 music tone output. Otherwise, the user can mix the wide-band noise and the CH1 music tone into one output through the MIXER. Lastly, the user can select 4 volume levels controlled by VOL0, VOL1. PSG as an Alarm Generator When PSG is in the alarm mode, the CH1 provides the alarm carrier frequency and the CH2 provides the alarm envelope signal. Lastly the user can select 4 volume levels controlled by VOL0, VOL1. The channel 2 low nibble C2.0 - C2.3 will be the alarm control register. Channel 1 output would modulate with an ALARM envelope control for 32.768kHz or 262kHz. The carrier frequency can be programmed by PSG channel 1.In reading this alarm control register, the user can read the corresponding output envelope frequency (the 1Hz, 4Hz, 8Hz, and 32Hz). Alarm Control Register (OSC = 32.768kHz or 262kHz) $373 C2.3 0 X X X 1 C2.2 0 X X 1 X C2.1 0 X 1 X X C2.0 0 1 X X X Alarm output control DC envelop 1Hz output 4Hz output 8Hz output 32Hz output
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Figure: Alarm modulation output for OSC = 32.768kHz or OSC = 262kHz.
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PSG as Remote Control The remote control is only an expandable application for PSG sound. The user can select the CH1 as tone output and the CH2 will create alarm frequency envelope signal. When PSG channel is programmed in the ALARM mode, the programmer can set ALARM mode register to "0000B". Program the adequate frequency output to PSG output. Then use PAM1 or PAM2 control the envelope of code. In this way, remote control function can be implemented easily. The Remote Frequency = 56.73kHz or 37.92kHz. The software should select OSCX = 455kHz, SEL1 = 1 and SEL0 = 0, so that the PSG Clock = 455kHz. Then select channel 1 alarm mode (C1M = 1), and OCT1 = 0, C2.0 - C2.3 are set to 00H. VOL1, VOL2 = 1, 1. Then select C1.6 - C1.0 = 7E, so that N = 6 and the PSG output frequency = 455kHz/1/(2 X 6) = 37.92kHz. Or select C1.6 - C1.0 = 78, so that N = 4 and the PSG output frequency = 455kHz/1/(2 X 4) = 56.87kHz.
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13. Interrupt Four interrupt sources are available in SH67P54: - External interrupt (INT0) - Timer0 interrupt - Base timer interrupt - Port's falling/rising edge detection interrupt (INT1) 13.1. Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program. Those flags are cleared to 0 at initialization by the chip reset. The Configuration of System Register $0: Address $00 $01 Bit 3 IEX IRQX Bit 2 IET0 IRQT0 Bit 1 IEBT IRQBT Bit 0 IEP IRQP Function Interrupt enable flags Interrupt request flags
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and the vector address will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be saved into the stack memory and jump to the interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx) are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and the vector address will be generated from the priority PLA corresponding to the interrupt sources.
Inst.cycle 1 2 3 4 5
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Instruction Execution N
Instruction Execution I1
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Vector Generated Stacking Fetch Vector address Reset IE.X
Instruction Execution I2
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Interrupt Generated
Interrupt Accepted
Start at vector address
Interrupt Servicing Sequence Diagram Interrupt Nesting: During the SH6610D CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated. 13.2. External Interrupt External interrupt is shared with the PORTA.0, falling/rising edge active. When the bit 3 of the register $0 (IEX) is set to 1, the external interrupt is enabled. The External interrupt can be used to wake the CPU from the HALT mode. 13.3. Timer0 Interrupt, Base Timer Interrupt The input clock of Timer0 and Base Timer are based on system clocks or OSC clock/INT0 input as Timer0 and Base Timer source. The timer overflow from $FF to $00 will generate an internal interrupt request (IRQT0 or IRQBT = 1), If the interrupt enable flag is enabled (IET0 or IEBT = 1), a timer interrupt service routine will start. Timer interrupt can also be used to wake the CPU from the HALT mode. 13.4. Port Interrupt The PORTB and PORTC are used as port interrupt sources. Since PORTB and PORTC are bit programmable I/Os, so only the voltage transition from VDD to GND applying to the digital input port can generate a port interrupt. The condition is that the other port must be input high level.
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14. HALT and STOP Mode After the execution of HALT instruction, the device will enter halt mode. In the halt mode, CPU will stop operating. But peripheral circuit (Timer0, Base Timer, and Watchdog Timer) will keep operating. After the execution of STOP instruction, the device will enter stop mode. In the stop mode, the whole chip (including oscillator) will stop operating without watchdog timer, if it is enabled. In HALT mode, SH67P54 can be waked up if any interrupt occurs. In STOP mode, SH67P54 can be waked up if port interrupt occurs or Watchdog timer overflow (when WDT is enabled). When SH67P54 is waked up by interrupt from HALT or STOP mode, it will save current PC into the stack and jump to the corresponding interrupt vector address. 15. Warm-up Timer The device has oscillator warm-up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the following conditions: - Hardware reset - Power on reset - Low voltage reset - Wake-up from stop mode Warm-up time interval: 7 (1) If RC oscillator is selected as system clock, the warm-up counter prescaler is divided by 2 (128). 7 Example: 262kHz RC is system clock, warm-up time interval is 2 X (1/262kHz) = 0.489ms. 12 (2) If Ceramic Resonator/Crystal Oscillator is selected as system clock, the warm-up counter prescaler is divided by 2 (4096). Example: 8MHz Ceramic is system clock, warm-up time interval is 212 X (1/8MHz) = 0.512ms.
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16. Options 16.1. Bonding Options Up to 4 different bonding options are possible for the user 's needs. The chip's program has 4 different program flows that will vary depending on which bonding option is used. The readable contents of BD1 and BD0 will be different depending on bonding. Address $0C PAM2 X X X X PAM1 X X X X
GND BD 0 BD 1
Bit 3
Bit 2
Bit 1 BD 1
Bit 0 BD 0
R/W R R/W
Remarks Bit0, 1: Bonding option. BD0 is weakly pulled high, BD1 is weakly pulled low. Bit2, 3: PORTA.1 & PORTA.2 as PSG output or I/O PORT BD1 bond to VDD BD0 bond to GND BD0 bond to GND and BD1 bond to VDD
GND
0 1 0 1
1 1 0 0
VDD
BD 0
BD 1
VDD
PCB
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BD 0 = 1 GND BD 0 BD 1 BD 1 = 0 BD 0 = 1 BD 1 = 1
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GND
VDD
BD 0
BD 1
VDD
PCB BD 0 = 0 BD 1 = 0 BD 0 = 0 BD 1 = 1
SH67P54 Bonding Option
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16.2. Code Option (a) Oscillate type: 0 = 32.768kHz Crystal oscillator 1 = 262kHz RC oscillator (b) OSCX range select: 0 = 400kHz - 2MHz 1 = 2MHz-8MHz (c) Watchdog timer: 0 = Enable 1 = Disable (d) LVR Reset 0 = Disable 1 = Enable (e) LVR level 0 = Level1: 4.0V 1 = Level2: 2.5V (f) LCD/LED matrix 0 = LCD application 1 = LED matrix application
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17. Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. Arithmetic and Logical Instruction Accumulator Type Mnemonic ADC ADCM ADD ADDM SBC SBCM SUB SUBM EOR EORM OR ORM AND X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx Function Flag Change CY CY CY CY CY CY CY CY
Mx + Ac + CY Mx + Ac + CY
Mx + Ac Mx + Ac Mx + -Ac + CY Mx + -Ac + CY Mx + -Ac + 1 Mx + -Ac + 1 Mx Ac Mx Ac Mx | Ac Mx | Ac Mx & Ac Mx & Ac
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ANDM SHR
0 AC [3]; AC [0] CY ; .com one bit AC shift right
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CY
Immediate Type Mnemonic ADI ADIM SBI SBIM EORIM ORIM ANDIM X,I X,I X,I X,I X,I X,I X,I Instruction Code 01000 i i i i xxx xxxx 01001 i i i i xxx xxxx 01010 i i i i xxx xxxx 01011 i i i i xxx xxxx 01100 i i i i xxx xxxx 01101 i i i i xxx xxxx 01110 i i i i xxx xxxx AC AC, Mx AC AC, Mx AC, Mx AC, Mx AC, Mx Function Mx + I Mx + I Mx + -I + 1 Mx + -I + 1 Mx I Mx | I Mx & I Flag Change CY CY CY CY
Decimal Adjust Mnemonic DAA DAS X X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx AC; Mx Function Flag Change CY CY
Decimal adjust for add. AC; Mx Decimal adjust for sub.
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Transfer Instruction Mnemonic LDA STA LDI X (, B) X (, B) X,I Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 i i i i xxx xxxx AC Mx Function Flag Change
Mx AC AC, Mx I
Control Instruction Mnemonic BAZ BNZ BC BNC BA0 BA1 BA2 BA3 CALL X X X X X X X X X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx 11010 000h hhh l l l l 11010 1000 000 0000 11011 1000 000 0000 X 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111 PC P PC Function Flag Change
PC PC PC PC PC P
PC
X X X X X X X X
if AC = 0 if AC 0 if CY = 1 if CY 1 if AC (0) = 1 if AC (1) = 1 if AC (2) = 1 if AC (3) = 1
ST P
CY; PC + 1 X (Not include p) CY
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RTNW H, L RTNI HALT STOP JMP TJMP NOP Where PC AC -AC CY Mx
PC ST; TBR hhhh; AC l l l l CY; PC ST
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11011 0000 000 0000 .com
X (Include p) (PC11 - C8) (TBR) (AC)
No Operation
Program counter Accumulator Complement of accumulator Carry flag Data memory
I
Immediate data Logical exclusive OR Logical OR Logical AND RAM bank = 000
p ST TBR
ROM page = 0 Stack Table Branch Register
| & bbb
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Electrical Characteristics
Absolute Maximum Ratings* DC Supply Voltage . . . . . . . . . . . . . . .-0.3V to +7.0V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . . -40 to +85 Storage Temperature . . . . . . . . . . . . -55to +125 DC Electrical Characteristics (VDD = 3.0V ,GND = 0V, TA = 25, fOSC = 32.768kHz, fOSCX is not used, LCD voltage divider resistor = 270k, 1/4 LCD bias, unless otherwise specified) Parameter Operating Voltage Operating Current Operating Current Standby Current Symbol VDD IOP1 IOP2 ISB1 ISB1H ISB2 VIH VIH1 VIL VIL1 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RON RPH RPL IWDT ILCD RLCD Min. 2.4 0.7 X VDD 0.8 X VDD -0.3 -0.3 0.7 X VDD 0.7 X VDD VDD - 0.6 VDD - 0.6 Typ. 3 12 Max. 6 22 Unit V A Conditions *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
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Standby Current Standby Current Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage LCD Driving on resistor Pull-high Resistor Pull-low Resistor WDT Current LCD Lighting LCD voltage divider resistor
All output pins unload execute NOP instruction, LCD off, WDT off All output pins unloaded, OSCX as system oscillator, 0.3 0.5 mA fOSCX = 4MHz (Execute NOP instruction) All output pins unload (HALT mode), WDT off, 4 6 A LVR off, LCD off All output pins unload, (HALT mode) OSCX as 200 300 A system oscillator, fOSCX = 4MHz WDT off All output pins unload (STOP mode), 1 A .com off, WDT off LCD 5 200 200 8 270 90 30 10 VDD + 0.3 VDD + 0.3 0.3 X VDD 0.2 X VDD 0.2 X VDD 0.2 X VDD 0.6 GND + 0.6 10 10 V V V V V V V V V V V V k PORTA - PORTD RESET (Schmitt trigger input) PORTA - PORTD RESET (Schmitt trigger input) PORTA.0, PORTA.3, PORTB - D (IOH = -2mA) PORTA.0, PORTA.3, PORTB - D (IOL = 2mA) PORTA.1 - 2 or Alarm output, IOH = -5mA PORTA.1 - 2 or Alarm output, IOL = 5mA SEGx to be output port or LED SEGx IOH = -1mA SEGx to be output port or LED SEGx, IOL = 1mA LED COMx, IOH = -100A LED COMx, IOL = 2.5mA LCD COMx, LCD SEGx, the voltage variation of V1, V2, V3, V4 is less than 0.2V
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k PORTA - D k PORTA - D A A RLCD1, RLCD0 = 0, 0 RLCD1, RLCD0 = 0, 1 k RLCD1, RLCD0 = 1, 0 RLCD1, RLCD0 = 1, 1
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DC Electrical Characteristics (VDD = 5.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, fOSCX is not used, LCD voltage divider resistor = 270k, 1/4 LCD bias, unless otherwise specified) Parameter Operating Voltage Operating Current Operating Current Standby Current Standby Current Standby Current Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Symbol VDD IOP1 IOP2 ISB1 ISB1H ISB2 VIH VIH1 VIL VIL1 RPH RPL IWDT ILCD Min. 2.4 0.7 X VDD 0.8 X VDD -0.3 -0.3 Typ 5 22 1.5 7 600 150 150 12 Max. 6 42 2 12 800 1 VDD + 0.3 VDD + 0.3 0.3 X VDD 0.2 X VDD 15 Unit V A mA A A A V V V V k k A All output pins unload execute NOP instruction, LCD off, WDT off All output pins unloaded, OSCX as system oscillator, fOSCX = 8MHz (Execute NOP instruction) All output pins unload (HALT mode), WDT off, LVR off All output pins unload, (HALT mode), OSCX as system oscillator, fOSCX = 8MHz WDT off All output pins unload (STOP mode), LCD off, WDT off PORTA - PORTD RESET (Schmitt trigger input) PORTA - PORTD RESET (Schmitt trigger input) PORTA - D PORTA - D Conditions
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Pull-high Resistor Pull-low Resistor WDT Current LCD Lighting
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AC Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 32.768kHz crystal, unless otherwise specified) Parameter Oscillation Start Time Instruction Time Symbol tSTT Tcy Min. Typ. 1 122.07 Max. 2 Unit s s Conditions
AC Characteristics (GND = 0V, TA = 25, fOSC = 262kHz RC, fOSCX stop, unless otherwise specified) Parameter Frequency Variation Symbol |f|/f Min. Typ. Max. 20 Unit % Conditions Include supply voltage and chip-to-chip variation
AC Characteristics (GND = 0V, TA = 25, fOSCX = 8MHz RC, unless otherwise specified) Parameter Frequency Variation Symbol |f|/f Min. Typ. Max. 20 Unit % Conditions Include supply voltage and chip-to-chip variation
Low Voltage Reset Electrical Characteristics (VDD = 2.4 - 6V, GND = 0V, TA = 25C, unless otherwise specified) Parameter LVR Voltage 1 LVR Voltage 2 Symbol VLVR1 VLVR2 Min. 2.4 3.8 Typ. 2.5 4.0 Max. 2.6 4.2 Unit V V LVR Enable LVR Enable Condition
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Timing Waveform System Clock Timing Waveform
T1
T2
T3
T4
T5
T6
T7
T8
T1
T2
T3
T4
System Oscillator
System Clock
Tcy
RC Oscillator Characteristics Graphs (for reference only) Typical RC Oscillator Resistor vs. Frequency: (1) fOSC vs. Rosc
VDD = 5.0V 500 400 fosc (kHz)
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300 200 100 0 0 1000 2000 3000 4000 Rosc (k) 5000 6000 7000 8000
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Resistor vs. fOSC, VDD = 5.0V
VDD = 3.0V 500 400 fosc (kHz) 300 200 100 0 0 2000 4000 Rosc (k) 6000 8000
Resistor vs. fOSC, VDD = 3.0V
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(2) fOSCX vs. Roscx
VDD = 5V 8000 6000 foscx (kHz) 4000 2000 0 0 50 100 Roscx (k) 150 200
Resistor vs. fOSCX, VDD = 5.0V
VDD = 3.0V 8000
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6000 foscx (kHz) 4000 2000 0 0 50 100 Roscx (k) 150 200
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Resistor vs. fOSCX, VDD = 3.0V
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In System Programming Notice for OTP
The In System Programming technology is valid for OTP chip. The Programming Interface of the OTP chip must be set on the user's application PCB, and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip. Of course, it's accessible bonding OTP chip only first, and then programming code and finally assembling other components. Since the programming timing of Programming Interface is very sensitive, therefore four jumpers are needed (VDD, VPP, SDA, SCK) to separate the programming pins from the application circuit as shown in the following diagram. Application PCB OTP Chip VPP VDD SCK SDA GND OTP Writer
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To Application Circuit Jumper
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The recommended steps are as following: (1) The jumpers are open to separate the programming pins from the application circuit before programming the chip. (2) Connect the programming interface with OTP writer and begin programming. (3) Disconnect OTP writer and short these jumpers when programming is complete. For more detail information, please refer to the OTP writer user manual.
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Application Circuit (for reference only) AP1: VDD = 3.0V OSC: Crystal oscillator 32.768kHz (Code Option) OSCX: Ceramic oscillator 455kHz PORTB: I/O PORTA.1, PORTA.2: ALARM output LCD: Internal LCD 1/8 duty, 1/4 bias
8 x 30 1/8 duty 1/4 bias 100p 10k 104 VDD RESET OSCXO OSCXI 455kHz
SH67P54
I/O 32.768kHz
PORTB OSCO OSCI
PORTA.1
100 BUZZER
PORTA.2
12p TEST GND
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AP2: VDD = 5.0V OSC: RC oscillator 262kHz (Code Option) LCD: Internal LCD 1/4 duty, 1/3 bias PORTA, PORTB: I/O PORTA.0: External interrupt
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4 X 34 1/4 duty 1/3 bias
VDD 10k RESET 104
OSCXI OSCXO
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I/O 930k 102
PORTA PORTB OSCO OSCI
PORTA.0
Ext.int
GND TEST
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AP3: VDD = 5.0V OSC: Crystal oscillator 32.768kHz (Code Option) OSCX: RC oscillator 1.8MHz PORTB, PORTC, PORTD: I/O PORTA.1: PSG output PORTA.2: PSG output
4 X 26 1/4 duty 1/3 bias
45k 10k 104 I/O PORTB PORTC PORTD OSCO OSCXO VDD RESET OSCXI 102 SPEAKER
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10k PORTA.1
8050
32.768kHz OSCI
PORTA.2
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12p TEST
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GND
AP4: Large LCD panel: If internal different bias resistor (10k, 30k, 90k, 270k) don 't meet request, user can use External LCD bias
1/4 Bias or 1/3 Bias Normal LCD pannel 1/4 Bias Large LCD pannel V1 Ext.R V2 SH67P54 V3 V2 SH67P54 Ext.R V3 Ext.R V4 Use internal bias resistors V4 V4 V3 Ext.R V2 SH67P54 Ext.R 1/3 Bias Large LCD pannel V1 Ext.R
V1
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Music Table 1. Following is the music scale reference table for channel 1 (or channel 2) under OSCX = 1.8MHz. (Up to 6 octaves are possible) Music scale data for 1.8MHz OSCX and SEL0 = SEL1 = 1 Note B1 C2 #C2 D2 #D2 E2 F2 #F2 G2 A2 #A2 B2 Ideal freq. 61.73 65.10 69.29 73.42 77.78 82.41 87.31 92.50 98.00 110.00 116.54 123.47 130.81 138.59 146.83 155.56 164.81 174.61 184.99 196.00 220.00 233.08 246.94 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 440.00 466.15 493.88 LSFR OCT1 (C1.6 - C1.0) /OCT2 (C2.14 - C2.8) 114 1 42 N 108 101 96 90 85 81 76 72 68 64 60 57 54 51 48 45 43 40 38 36 34 32 30 28 27 25 24 23 21 20 19 18 17 16 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 23 64 0B 4E 54 4F 74 43 38 9 13 1B 5A 56 37 3D 76 31 46 1A 69 25 17 5D 3B 6E 5C 39 66 4C 19 32 65 4A 15 2A Real freq. 61.68 65.10 69.62 73.24 78.13 82.72 86.81 92.52 97.66 103.40 109.86 117.19 123.36 130.21 137.87 156.25 163.52 175.78 185.03 195.31 206.80 219.73 234.38 251.12 260.42 281.25 292.97 305.71 334.82 351.56 370.07 390.63 413.60 439.45 468.75 502.23 Error% Note -0.08 0.01 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.40 -0.13 0.56 -0.09 -0.46 -0.52 0.44 -0.79 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 B4 C5 #C5 D5 #D5 E5 F5 #F5 G5 A5 #A5 B5 C6 Ideal freq. 493.88 LSFR Real OCT1/ Error% (C1.6 - C1.0) freq. OCT2 (C2.14 - C2.8) 114 0 42 493.42 -0.09 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 64 0B 4E 54 4F 74 43 38 9 13 1B 5A 56 37 3D 76 31 46 1A 69 25 17 5D 3B 6E 5C 39 66 4C 19 32 65 4A 15 2A 520.83 556.93 585.94 625.00 661.77 694.44 740.13 781.25 827.21 878.91 937.50 986.84 1041.67 1102.94 1171.88 1250.00 1308.14 1406.25 1480.26 1562.50 1654.41 1757.81 1875.00 2008.93 2083.33 2250.00 2343.75 2445.65 2678.57 2812.50 2960.53 3125.00 3308.82 3515.63 3750.00 4017.86 -0.46 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.41 -0.12 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.78 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69
523.25 108 554.35 101 587.33 622.24 659.26 698.46 739.97 783.99 880.00 932.31 987.77 96 90 85 81 76 72 68 64 60 57 51 48
#G2 103.82
#G5 830.59
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C3 #C3 D3 #D3 E3 F3 #F3 G3 A3 #A3 B3 C4 #C4 D4 #D4 E4 F4 #F4 G4 A4 #A4 B4
1046.48 54
#C6 1108.71
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E6 F6
#D6 1244.48 45 1318.48 43 1396.88 40
#F6 1479.95 38 G6 1567.95 36 #G6 1661.18 34 A6 B6 C7 D7 E7 F7 1759.96 32 1975.49 28 2092.96 27 2349.27 24 2636.96 21 2793.77 20 #A6 1864.62 30
#G3 207.65
#C7 2217.41 25 #D7 2488.96 23
#F7 2959.89 19 G7 3135.90 18 #G7 3322.37 17 A7 B7 3519.93 16 3950.98 14 #A7 3729.23 15
#G4 415.30
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Music Table 2. Following is the music scale reference table for channel 1 (or channel 2) under OSC = 32.768kHz. (Up to 4 octaves are possible) Music scale data for 32.768kHz OSC and SEL0 = SEL1 = 0 Note A1 #A1 B1 C2 #C2 D2 #D2 E2 F2 #F2 G2 A2 Ideal freq. 55.00 58.27 61.73 65.41 69.29 73.42 77.78 82.41 87.31 92.50 98.00 110.00 116.54 123.47 130.81 138.59 146.83 164.81 174.61 184.99 196.00 220.00 233.08 246.94 N 37 35 33 31 30 28 26 25 23 22 21 20 19 18 17 16 15 112 99 94 89 84 79 74 70 66 LSFR OCT1 (C1.6 - C1.0) /OCT2 (C2.14 - C2.8) 1 0D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 34 52 4B 17 5D 77 6E 39 73 66 4C 19 32 65 4 0C 0A 1E 11 2C 1D 29 3E 50 0E 62 Real freq. 55.35 58.51 62.06 66.07 68.27 73.14 78.77 81.92 89.04 93.09 97.52 102.40 107.79 113.78 120.47 136.53 146.29 156.04 165.50 174.30 184.09 195.05 207.39 221.41 234.06 248.24 Error% Note 0.64 0.42 0.54 1.00 -1.48 -0.38 1.27 -0.60 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -1.48 -0.37 0.31 0.42 -0.18 -0.49 -0.49 -0.12 0.64 0.42 0.53 C4 #C4 D4 #D4 E4 F4 #F4 G4 A4 #A4 B4 C5 #C5 D5 E5 F5 #F5 G5 A5 #A5 B5 Ideal freq. 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 440.00 466.15 493.88 523.25 554.35 587.33 659.26 698.46 739.97 783.99 880.00 932.31 987.77 N 63 59 56 53 50 47 44 42 39 37 35 33 31 30 28 26 25 23 22 21 20 19 18 17 15 14 LSFR Real OCT1 Error% (C1.67 - C1.0) freq. /OCT2 (C2.14 - C2.8) 0 12 260.06 -0.60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 36 35 2D 6F 7B 6C 63 0D 34 52 4B 17 5D 77 6E 39 73 66 4C 19 32 65 4A 15 2A 277.70 292.57 309.13 327.68 348.60 372.36 390.10 420.10 442.81 468.11 496.49 528.52 546.13 585.14 630.15 655.36 712.35 744.73 780.19 819.20 862.32 910.22 963.77 1024.00 1092.27 1170.29 0.19 -0.37 -0.64 -0.59 -0.18 0.64 -0.49 1.16 0.64 0.42 0.53 1.01 -1.48 -0.37 1.27 -0.59 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37
#G4 415.30
#G2 103.82
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#A2 B2 C3 #C3 D3 #D3 E3 F3 #F3 G3 A3 #A3 B3
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155.56 105
#G5 830.59
#G3 207.65
C6 1046.48 16 #C6 1108.71 D6 1174.63
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Bonding Diagram
COM8/SEG31 COM7/SEG32 COM6/SEG33 COM5/SEG34
SEG25
SEG27
SEG29
SEG26
SEG28
SEG30
COM4
COM3
COM2
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
42 41 40 39 38 37 36 35 34 33 32 31 30 29
COM1
28 27
V1 V2 V3 V4 RESET TEST OSCO OSCI OSCXO 1956 um
Y
26 25
SH67P54 X (0,0)
24 23 22 21 20
19 OSCXI 18
VDD
BD1 BD0
GND 17
1 PORTD.3/SEG8
2 PORTD.2/SEG7
3 PORTD.1/SEG6
4 PORTD.0/SEG5
5 PORTC.3/SEG4
6 PORTC.2/SEG3
7 PORTC.1/SEG2
8 PORTC.0/SEG1
9 PORTB.3
10 PORTB.2
11 PORTB.1
12 PORTB.0
13 PORTA.3
14 PORTA.2
15 PORTA.1
16 PORTA.0
2162 um
Substrate connects to GND. Pad Location Pad NO. Designation PORTD.3/SEG8 PORTD.2/SEG7 PORTD.1/SEG6 PORTD.0/SEG5 PORTC.3/SEG4 PORTC.2/SEG3 PORTC.1/SEG2 PORTC.0/SEG1 PORTB.3 PORTB.2 PORTB.1 PORTB.0 PORTA.3 PORTA.2 PORTA.1 PORTA.0 GND BD0 VDD BD1 OSCXI OSCXO OSCI OSCO TEST RESET V4 V3 V2 V1 X (m) -874 -739 -610 -485 -360 -235 -110 15 140 265 385 505 625 745 875 1005 873 969 969 969 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 Y (m) Pad No. Designation COM1 COM2 COM3 COM4 COM5/SEG34 COM6/SEG33 COM7/SEG32 COM8/SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 X (m) 666 546 426 311 196 81 -34 -149 -264 -379 -499 -619 -749 -879 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 unit: m Y (m) 908 908 908 908 908 908 908 908 908 908 908 908 908 908 902.5 772.5 642.5 522.5 402.5 287.5 172.5 57.5 -57.5 -172.5 -287.5 -402.5 -522.5 -642.5 -772.5 -902.5
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
-908 29 -908 30 -908 31 .com -908 32 -908 33 -908 34 -908 35 -908 36 -908 37 -908 38 -908 39 -908 40 -908 41 -908 42 -908 43 -908 44 -581 45 -581 46 -365 47 -461 48 -235 49 -120 50 -5 51 110 52 225 53 342.5 518 648 778 908 54 55 56 57 58
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Ordering Information
Part No. SH67P54H-yyxxx/000HR SH67P54F-yyxxx/064FR Package CHIP FORM QFP 64L Packing Tray Tray
Note: (1) "-yyxxx": "yy" means 2 bits option and "xxx" means 3 bits code seriary number. If the product is OTP type and in blank order, those bits should be none. (2) The data after mark "/" in Part No. block is the package and packing information for ordering. (3) The size of those package types are showed in "Package Information" (Page51). (4) Any other package or packing request, please refer to following table. Package D F H J K L DIP QFP CHIP CER-DIP SKINNY PLCC SOP OTHER GOOD DIE ON WAFER SOJ TO92 VSOP/TSOP WAFER TSSOP R U A D L B T S N Packing Normal package size and in tray packing Normal package size and in tube packing Normal package size and in tape & reel packing Larger package size and in tray packing Larger package size and in tube packing Larger package size and in tape & reel packing Smaller package size and in tray packing Smaller package size and in tube packing
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M N Q S T V W X
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Package Information
QFP 64L Outline Dimensions
HD D 64 1 52 51
unit: inches/mm
19 20 b 32
33
e GD
HE
GE
E
GD c
~ ~ ~
A2 See Detail F Seating Plane
A
y
D
A1
L L1
Detail F
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Symbol A A1 A2 b c D E e GD GE HD HE L L1 y
Dimensions in inches 0.004 Min. 0.112 0.005 0.016 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.039 0.006 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max. 0 - 12
Dimensions in mm 3.30 Max. 0.10 Min. 2.85 0.13 0.40 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 1.00 0.15 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max. 0 - 12
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Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
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Data Sheet Revision History
Version 1.0 Original Content Date
Oct. 2004
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